The present invention relates generally to integrated circuit memory devices and, more particularly, to a write/read priority blocking scheme using a parallel static address decode path.
Generally, electronic circuits have significant data storage capacities. Such capacities may be achieved with large memories formed of several memory blocks for physical or logical reasons. For example, such memories may include SRAM (Static Random-Access Memory) or DRAM (Dynamic Access Memory). A memory controller enables the other functions of the electronic circuit to view all the memory blocks as a single memory, in terms of address.
In one implementation, memory blocks may have a single-port architecture. In other words, as seen from the other electronic circuit functions, a single-port block can only perform one read operation or one write operation at a time. This memory block architecture avoids the need for overly complex memory architectures or architectures consuming too much circuit surface area. On the other hand, it may sometimes be desirable for some functions of the electronic circuit to simultaneously perform a read operation and a write operation. In this case, other architectures, such as two-port, dual-port, and multiple port cells have also become popular.
For memory architectures performing address decoding that are presented with both read and write addresses at the same bank of logical entries, a banking function can be performed, which enables simultaneous read and write operations to different memory banks. In the case of multiport arrays, simultaneous reads to any logical entry can be achieved. However, in the case of a bank conflict where a request is made for simultaneous read and write to the same logical bank, a decision must be made to determine whether the access will be a read or a write. This decision can be made external to the memory array, in which case the desired address is simply sent to the memory without a conflict; however, the memory array could also perform this function with the appropriate logic if it is known whether reading or writing takes priority.
In the case of a write access taking priority over a read access, the write address can be used to prevent a full read address decode when the read and write addresses are the same. One approach would be to use the actual write decode in the critical decode path for the address blocking; however, this would introduce timing complexity in the critical path, specifically loading down the partially decoded write MSB signals with additional wire and device load. As a result, the write decode path timing would start to differ from that of the read decode path, and such a difference would worsen across process variations.